Innovations in deep-submicron CMOS technology allow integrated digital circuitry to operate at clock speeds in the gigahertz range. These high clock rates demand a corresponding increase in the speed of input/output (I/O) signals that are transmitted over interconnect lines between various IC components, such as central processing units (CPU), I/O processing units, and high-speed memory, which implement various system functions. At rates of 6 Gb/s and beyond, impairments in electrical interconnect channels for interchip communications can result in significant signal degradation, due to time dispersion, reflections, and crosstalk and other undesirable electrical phenomena, which can prohibit robust data transfer when using I/O core designs based on receive threshold comparators.
State of the art serial I/O core designs typically implement adaptive line equalization systems to eliminate or otherwise mitigate distortion of I/O signals that can occur in high-speed electrical channels. In general, a line equalizer system may use linear equalization control systems that compensate frequency dependent phase distortion and amplitude fluctuations that occur in high speed electrical channels. In other frameworks, a line equalizer system may implement non-linear equalization control methods using a decision-feedback equalizer (DFE) configured to remove data-dependent inter-symbol interference (ISI) from a received data stream and improve the performance of reliable data detection. Typically, state of the art serial I/O transceiver architectures employ a combination of transmit and/or receive linear equalizer and receive non-linear equalizer to achieve optimal system performance.
For example, FIG. 1 schematically illustrates a conventional data transceiver system that implements transmit and receive line equalization. In particular, FIG. 1 illustrates a data transceiver system (100) having a high-speed serial link serializer/deserializer system (SERDES) commonly used for high speed I/O system designs. The data transceiver system (100) comprises a data transmitter (100A) and a data receiver (100B), wherein the transmitter (100A) transmits serial data to the receiver (100B) over a communications channel (100C). In general, the transmitter (100A) includes a serializer block (110) to serialize an input parallel data block (105), a feed-forward equalizer (FFE) (115) to pre-distort the serial data, and a buffer/amplifier (120) to drive the communications channel (100C) and output the serialized data stream to the receiver (100B). The transmitter (100A) transmits serial data to the receiver (100B) over the communications channel (100C) at a much higher rate than a core clock that generates the parallel data streams (105) (which clock rate is typically 8, 10, or 16 times slower than the serial bus data rate).
The receiver (100B) generally includes an input buffer/amplifier (125) which buffers and amplifies a received serial data stream, a feed-forward equalizer (130), a summing block (135), a decision-feedback equalizer (DFE) (140), a data slicer (145), a clock generator (150), and a data de-serializer (155) that outputs a parallel data stream (160). In the example diagram shown in FIG. 1, the clock generator (150) is a 3-phase clock generator that produces edge E, data D, and amplitude A clock signals to drive corresponding Edge, Data, and Amplitude slicers in the slicer circuit (145). The sampled data signal output from the Data slicer of slicer block (145) is deserialized via the DESER block (155). The E and D binary outputs of the slicers (145) are processed by clock generator (150) using adaptive time alignment designed to maintain phase coherence of the local clocks with respect to the received data, and the A and D outputs of the slicer block (145) are processed by the DFE (140) to remove distortion arising from inter-symbol interference (ISI) in the channel. Details of a FFE/DFE line equalization system for high-speed I/O designs using the architecture of FIG. 1 are well known in the art.
A key challenge with line equalization systems is to determine optimum sampling points for the local clocks and optimum settings for linear (FFE) and/or DFE equalizers. There are well-established techniques for clock recovery, using common “early-late” clock-and-data recovery, which lock an “Edge” clock to a received data waveform, and then derive a data clock from a fixed time offset (typically ½ bit) from the “Edge” clock. At higher data rates, however, systematic timing errors in the clocks may arise due to circuit variability or line characteristics, which result in non-optimum data strobe points and degrade system performance. In addition, well-established techniques exist to adapt linear and DFE equalizers using sign-sign LMS adaptation techniques, but at high serial data rates in the 6 to 12 Gb/s range, small absolute timing errors in clock distribution or data path delays result in enough systematic error to degrade system performance of prior-art designs based on fixed offset clock generation. The term “open loop” clock generation system as used herein generally refers to a system that generates sample clock phases with fixed relative time offsets.
FIG. 2 schematically illustrates a conventional receiver system (200) with fixed linear equalizer and adapted DFE, which may be implemented in the receiver system (100B) of FIG. 1. FIG. 2 schematically illustrates a conventional framework of a sign-sign LMS-based adaptation system for a receiver, which employs an “open loop” clock generation system. In general, the receiver system (200) comprises a linear equalizer (201) that is controlled by a Fixed_Peak_Level control setting, summing blocks (202, 203, 204), sampling latches (207, 208, 209), a multiplier block (210), a phase offset block (211), a DFE Adapt control block (205), and a CDR (clock data recovery) Adapt control block (206). An input serial data stream is process through the front-end linear equalizer (201) with fixed peak level, and output to the summing circuits (202, 203, 204). The outputs of the summing circuits (202, 203, 204) are data inputs to respective latch circuits (207, 208, 209). The latch (209) serves to sample respective data at an edge or crossover time of the received data waveform (E sample), the latch (208) serves to sample at a data sample time (D sample) and latch (207) sample at a data sample time with a summed offset to the received waveform (A sample).
The DFE ADAPT block (205) receives as input D and A samples output from respective latches (207) and (208) to determine an A OFFSET value that is output to the summation block (202), which results in provision of a sign error (A) capable of driving a sign-sign LMS adaptation for FFE and/or DFE equalization. In FIG. 2 a 1-tap DFE is shown which is realized by multiplying (210) an adapted D OFFSET value by a previously detected data bit D and adding (203) the result to a D path waveform for the next sample.
The clock-and-data recovery (CDR) adaptation loop (206) receives as input D and E samples from respective latches (208) and (209) and creates a CLK_E sampling clock, which is phase and frequency locked to the input data waveform. This CLK_E sampling clock is offset by a phase D/E OFFSET (211) to derive a data sample clock CLK_D and amplitude sample clock CLK_A. The D/E OFFSET signal may be computed as a variable value as a function of line equalization parameters using known methods, but since the variable value is deterministic with respect to line equalization parameters it is considered an “open-loop” clock phase generation system.
A conventional receiver system such as shown in FIG. 2 has an “open loop” sampling clock framework that uses clock signals with fixed relative phase relationships with respect to each other and with respect to an incoming data waveform. As an example, the edge clock phase in a “early-late” phase detector based system has a phase relationship equal to the median time crossing of the received signal (with a potential added systematic bias), and the data clock phase is normally fixed with respect to the edge clock phase at either a constant offset or a variable offset dependent on the receiver equalization setting.
This fixed FFE/adapted DFE system using “open loop” clocking can provide good performance for systems operating in the range of 5 to 6 Gb/s. However, as data rates approach 10 Gb/s and beyond, systematic error in the sampling time of the sampling clocks arising from circuit non-idealities and characteristics of the received waveform due to channel imperfections can result in non optimum convergence of the equalizer, in particular the first feedback tap weight of a DFE. As an illustrative example, at a data rate of 10 Gb/s, only 10 ps of systematic timing error is needed to offset the sampling clock enough to move 10% of the unit interval width. As the clock error fluctuates due to variables which are difficult to control such as device variability during manufacturing or variation due to voltage and temperature fluctuations during operation, the optimality of the data, edge, and amplitude sampling points is reduced, resulting in mis-converged DFE adaptation, off-center data sampling, and overall degraded system performance. Further, a fixed linear equalizer setting prior to the DFE is not optimal for the wider range of channel gain variation, which can easily occur at higher data rates.